Intel Sees Efficiency, Density Scaling Far Beyond CMOS

Conventional CMOS scaling has entered a state of terminal decline. That’s the bottom-line takeaway, when you cut through the marketing spiel from companies and look at the expected improvements offered at future nodes. 7nm will still offer a significant improvement over 16/14nm, 5nm is expected to deliver smaller (though still noticeable) gains, and past that point, all bets are off. There are concerns that nodes below 5nm may not be commercially sustainable, both because the gains are shrinking as costs rise and because the number of customers willing to pay the premiums grows smaller every cycle, requiring that higher costs be borne by a smaller number of firms.

We’ve seen any number of proposals that could yield short-term benefits, such as adopting microfluidic cooling channels or superior heat-transference materials within the CPU itself, but no opportunities for gains that would ignite scaling improvements in a manner even approaching the Good Old Days of Moore’s law and Dennard scaling.

Today, Intel researchers published a paper in Nature that might point the way towards a solution to this seemingly intractable state of affairs. On the one hand, this is genuinely exciting news. As the paper states:

Here we propose a scalable spintronic logic device that operates via spin–orbit transduction (the coupling of an electron’s angular momentum with its linear momentum) combined with magnetoelectric switching. The device uses advanced quantum materials, especially correlated oxides and topological states of matter, for collective switching and detection… [I]n comparison with CMOS technology our device has superior switching energy (by a factor of 10 to 30), lower switching voltage (by a factor of 5) and enhanced logic density (by a factor of 5). In addition, its non-volatility enables ultralow standby power, which is critical to modern computing.

This could — and I emphasize could — be one of the first steps towards the resumption of something resembling ‘classic’ semiconductor scaling. One reason why we haven’t seen manufacturers move towards adopting certain processes and potential improvements is that the gains require significant investment or manufacturing changes for what are essentially one-time improvements. What semiconductor firms want is a roadmap that promises to yield improvements in both the short-and-long term. After evaluating more than 25 proposals for beyond CMOS computing, Intel believes MESO — that’s the name for this new architecture, short for magnetoelectric spin orbit — holds the most long-term promise for improving voltage scaling, interconnect scaling, energy efficiency improvements, and scaling over multiple generations.

The device is built from a magnetoelectric switching capacitor, a ferromagnet, and a spin-to-charge conversion module. Spintronics (a portmanteau of “spin transport electronics”) focuses on using the spin of an electron and its magnetic moment as a means of performing computational activity. Spintronic devices have much lower power consumption requirements than conventional machines and can hold data in-memory without spending energy to do it. Intel has reportedly reduced the voltage needed for a multiferroic material from 3V to 500mV and believe they could reduce it further, down as far as 100mV. That’s vastly below anything in-use today.

Intel’s MESO has another advantage over CMOS — it can drastically reduce power consumption required for interconnects. We spoke to Sasikanth Manipatruni, director of Functional Electronics Integration and Manufacturing at Intel and lead author of the paper. According to him, interconnect power accounts for as much as 50 percent of a CPU’s overall power consumption depending on what the chip is doing. Difficulties in scaling interconnect speed and overall performance are a critical component of the so-called ‘memory wall’, or the gap between CPU clocks and off-die memory performance. Process node shrinks have long since stopped being helpful to the copper wires inside microprocessors, which is part of why AMD’s upcoming 7nm Epyc CPUs opted to toss all of its I/O and DRAM controllers into a dedicated 14nm die and use 7nm for the CPU cores themselves.

But MESO doesn’t rely on the resistance and capacitance of tiny wires — and that means it isn’t constrained by the same performance factors or issues. Its resistance requirements are 20-100x less stringent than conventional interconnects, while its capacitance requirements are 100x less stringent. According to Manipatruni, MESO could cut interconnect power by an order of magnitude compared to conventional approaches.

It isn’t currently clear how much additional raw performance would be gained by adoption of these computing methods. Intel’s own work indicates equivalent performance between a 0.1v MESO device and a low-leakage, low-power CMOS device with a 0.3V input voltage, but these are both ultra-low-power products to begin with. Then again, saving power in one area of device design frequently gives developers room to use it elsewhere. MESO and conventional CMOS circuits could theoretically be used in the same chip, allowing for selective improvement in some areas of operation without requiring an entire design to be built this way.

The Inevitable Caveats

I would caution against assuming any of this work will appear in products in the near future. Historically, it takes 12-15 years from the date of a breakthrough to when that breakthrough has tended to appear in shipping products, as the graph below illustrates:

A shift to MESO from CMOS would be a larger jump than any of these, but it represents a potential path forward beyond the adoption of domain-specific architectures (specialized AI chips and GPUs are both examples of the latter).

“MESO is a device built with room temperature quantum materials,” said Manipatruni. “It is an example of what is possible, and hopefully triggers innovation across industry, academia and the national labs. A number of critical materials and techniques are yet to be developed to allow the new type of computing devices and architectures.”

Intel has also been working on this project for eight years. But there’s a huge number of discoveries and advances that need to happen before any kind of commercialized product would ever come to market. In the near-term, we’re still stuck with 7nm, 5nm, and whatever might come beyond 5nm, assuming a viable and economically profitable path forward can be found.

The amount of ground still to be covered between the MESO devices Intel discusses in Nature and, say, a Core i9-9900K can’t be understated. But the fact that Intel thinks it may have found a path forward to enable device area scaling again, reduce interconnect power, and dramatically slash power consumption is significant, if only for this reason: It’s the first time in years that we’ve heard anyone make such a claim that didn’t rely on huge advances in a problematic emerging research material like graphene (or “graphene“). There are clearly hurdles and issues still to be worked through with MESO and it’s possible that some of these might be significant enough to prevent commercialization, but it still seems like a promising approach.